1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly to a method and structure for slowing down dopant diffusion in strained Si/Ge substrates for junction formation for devices (e.g., N-MOS devices) in strained Si/SiGe substrates.
2. Description of the Related Art
Strained Si complementary metal oxide semiconductor (CMOS) devices with a strained Si channel on a relaxed Si1-xGex buffer layer offer better device performance over conventional Si CMOS because of the enhancement in both channel electron and hole mobilities, and have been demonstrated for devices as small as about 60 nm (e.g., see FIG. 1 showing a structure 100 including a gate 110, an oxide spacers 120 formed on each side of the gate 110, and an extension junction region 130 formed in the vicinity of the oxide spacer 110).
However, for devices with Leff at about 60 nm or below, an extension junction depth Xj ˜30 nm or below would be needed. The diffusion of a dopant in SiGe can form parasitic barriers at the heterojunction in a heterojunction bipolar transistor (HBT).
More importantly, the junction slope Xjs near the channel region should be abrupt (<6 nm/decade), and the dopant concentration at the extension 130 should be ˜1E20/cm3.
However, the present inventors have recognized that these shallow junction requirements are difficult to achieve for a dopant (e.g., arsenic) junction in N-type metal oxide semiconductor (NMOS) devices in strained Si/Si1-xGex substrates due to significant arsenic-enhanced diffusion.
That is, experimentally, it has been found that arsenic dopant diffusivity increases exponentially with the percentage of the Ge content in the Si1-xGex buffer layer.
Thus, the present inventors have recognized that this enhanced arsenic dopant diffusion in strained Si/Si1-xGex substrates becomes a significant roadblock for generating ultra-shallow junctions for a small (e.g., about sub-50 nm) NMOS device in strained Si substrates where high % Ge (e.g., >about 20%) is used for higher electron and hole mobility for improved device performance.
In addition, for a sub-50 nm device, the enhanced lateral arsenic dopant diffusion will short-circuit (e.g., see FIG. 1) the source and drain regions of the NMOS device, and will render the device totally inoperable.
That is, as shown in FIG. 1, arsenic dopant concentration at about 1E19/cm3 and about 1E19 cm3 are immediately below the center of the gate 110 (e.g., a polysilicon gate). This high concentration of dopant underneath the gate indicates shorting due to enhanced arsenic junction diffusion from the extension junction region 130 to the gate region 110.
Thus, the present inventors have recognized that, prior to the present invention, there have been no known techniques (or resulting structures) for slowing down the arsenic enhanced diffusion in strained Si/Si1-xGex or Si1-xGex/Si device substrates.